Field effect transistors are widely employed to design various simulation circuits, for example, applied to an amplifier circuit, a biasing circuit or a step-down circuit, a starting circuit, or a variable resistance, and so on. As an emerging demand for high voltage devices, how to improve breakdown voltage of various kinds of field effect transistors has become a design target of high voltage field effect transistor.
For MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a DMOS (Double-diffused MOS) employing a planar diffusion technology is provided with characteristics such as a high current drive capacity, a low on-resistance, and a high breakdown voltage, such that DMOS is widely employed by power devices. Wherein, because LDMOSFET (Lateral Double-diffused MOSFET) is more compatible with CMOS technology, such that DMOS is widely employed. Normally, the DMOS device is provided with a drift region between an active region and an drain region, and a impurity concentration of the drift region is relative low. When the LDMOS is connected to a high voltage, because the drift region has a high impendence, the drift region can withstand a relative high voltage. In addition, the polycrystalline layer or metal layer of the LDMOS extends above an oxygen region of the drift region, and serves as a field electrode plate, thereby weakening a surface electric field of the drift region, and benefiting for improving a breakdown voltage.
For JFET, it is different from the LDMOSFET, the drain electrode voltage of the JFET is applied to the PN junction of the drain electrode and the gate electrode, and the breaking point is normally located within the body, not on the surface. So the breakdown voltage of the JFET cannot be improved either by a filed electrode or by other types. So, the conventional JFET is limited by PN junction, and the breakdown voltage is about 20˜30 volts, thereby limiting an application of JFET in high voltage field.
However, for emerging high voltage semiconductor integrated circuit technology, not only high voltage MOS transistor, but also high voltage JFET having high breakdown voltage and being compatible with CMOS/LDMOS integrated circuit producing technology are required, so as to meet a requirement of chips such as power management chips.